1. Field of the Invention
The present invention relates to a liquid crystal driving apparatus.
2. Description of the Related Art
There is generally known a liquid crystal driving apparatus driving a liquid crystal display panel (e.g. TFT) with a plurality of row electrodes and a plurality of column electrodes that includes a gate driver for driving a plurality of the row electrodes, and a source driver for driving a plurality of the column electrodes (see Japanese Patent Laid-Open Patent Publication No. 2004-274335).
FIG. 7 is a block diagram of a liquid crystal display panel, a gate driver, and a source driver.
As shown in FIG. 7, a liquid crystal display panel 100 includes a plurality of column electrodes 101 and a plurality of row electrodes 102 that are intersected by the plurality of column electrodes 101, and a plurality of FETs 103, each of which is arranged at a position of each of intersections between a plurality of the column electrodes 101 and the row electrodes 102. A gate and a source of each FET 103 are respectively connected to the row electrode 102 and the column electrode 101 at a position where these electrodes intersect each other. A capacitor 104 to be charged with electric charge for displaying is provided between a drain of each FET 103 and ground. A source driver 105 outputs a signal for driving all the column electrodes 101 for one row intersected by each of the row electrodes 102. When a gate driver 106 selectively outputs a signal for driving the row electrodes 102 for one row, the electric charge is charged in the capacitors 104 connected to the FETs 103 of all the column electrodes 101 for one row. By repeating the above-described processing, which is performed row by row, for all the rows of the liquid crystal display panel 100, the liquid crystal display panel 100 is enabled to display an image.
FIG. 8 is a block diagram showing an example of the source driver 105 shown in FIG. 7.
The source driver 105 includes a data register 200, latch circuits 201 and 204, latch pulse generating circuits 202 and 203, a digital-to-analog (D/A) converter 205, and a source output circuit 206.
The latch circuit 201 latches m bits of data. Here, m is a number obtained by multiplying the number of the column electrodes 101 in all the column electrodes 101 for one row intersected by each of the row electrodes 102 in the liquid crystal display panel, by a bit number j that is a digital value of each row electrode in the D/A converter 205. The latch circuit 201 includes latch areas 201-1 to 201-x in which m bits are divided into groups of n bits, and sequentially latches n bits of data until m bits of data are latched into the latch area selected from the latch areas 201-1 to 201-x. 
The data register 200 holds n bits of data that are an object to be latched into the latch areas 201-1 to 201-x of the latch circuit 201 and externally supplied at an appropriate timing. These n bits of data include display data for driving the column electrodes 101 of the liquid crystal display panel 100 to display. The latch pulse generating circuit 202 generates latch pulses LP1 to LPx which designate one of the latch areas 201-1 to 201-x every time the data register 200 holds n bits of data. By sequentially generating the latch pulses LP1 to LPx, m bits of data are latched into the latch circuit 201.
The latch circuit 204 latches m bits of data latched in the latch circuit 201. The latch pulse generating circuit 203 generates a latch pulse LP′ every time the latch circuit 201 latches m bits of data. By generating the latch pulse LP′, m bits of data in the latch circuit 201 are latched into the latch circuit 204.
The D/A converter 205 converts a digital value of m bits of data latched in the latch circuit 204 into an analog value thereof. The source output circuit 206: performs a signal processing, such as amplifying a voltage of an analog signal output from the D/A converter 205 to a sufficient level for driving the FET 103; and thereafter, applies the signal-processed signal to the source electrode of the FET 103 connected to the column electrode 101.
In other words, every time n bits of data are held in the data register 200, the latch pulses LP1 to LPx are generated by the latch pulse generating circuit 202 in an appropriate order, and the n bits of data are latched into one of the designated area 201-1 to 201-x in the latch circuit 201. Every time m bits of data in all latch areas are latched in the latch circuit 201, the latch pulse LP′ is generated, and m bits of data are latched into the latch circuit 204. The D/A converter 205 and the source output circuit 206 perform the signal processing for m bits of data latched in the latch circuit 204, to be output as a signal for driving all the column electrodes 101 for one row.
However, if extraneous noise such as noise causing a logic circuit included in the latch pulse generating circuit 202 to malfunction is supplied to the latch pulse generating circuit 202, a latch pulse may not be generated for a latch area, into which n bits of data should originally be latched, of a plurality of the latch areas 201-1 to 201-x making up the latch circuit. In such a case, since bits of the display data do not become in a one-to-one correspondence with the column electrodes, there are problems such that the liquid crystal display panel 100 is unable to display a desired image.